Customized integrated circuits that implement complex data processing and control systems provide significant cost advantages over systems constructed from standardized packaged components that are interconnected on printed circuit boards and the like. These customized circuits can be viewed as being constructed from a number of standardized processing blocks that are connected together by buses on a single silicon chip. The size of these circuits as well as the clock rates used in the individual processing blocks has steadily increased over time. As a result, it has become difficult to synchronize all of the computations to a single processing clock. Accordingly, a class of customized integrated circuits in which the individual processing blocks utilize synchronous processing based on a local clock and communicate with each other asynchronously has evolved.
The combination of this semi-asynchronous system design and a three-dimensional integrated circuit design holds the promise of providing substantial improvements in the size and complexity of such customized integrated circuits. In the following discussion, a large semi-asynchronous system will be referred to as a “system on a chip” or SOC. For example, one class of three-dimensional integrated circuit is constructed by stacking individual chips utilizing high-density vertical interconnections. When a SOC is constructed in such a three-dimensional structure, the effective size of the SOC is greatly increased, because the length of the bus line connecting the various components can be substantially reduced because the individual components are separated by smaller distances in space.
However, as the size of an SOC increases, other problems are encountered. First, the yield of devices decreases because of defects in either the individual processing blocks or the bus lines connecting these blocks. To overcome this problem in large circuits, redundant blocks can be included in integrated circuits that are constructed from blocks that are present in large numbers. For example, large memories are constructed from a large number of small memory blocks that are connected to a common bus. These spare blocks are used to replace blocks that are found to be defective when the devices are tested. In conventional two dimensional circuits in which the individual components are wired to a common bus and the circuit elements are accessible to the re-wiring equipment, the defective blocks can be removed by disconnecting the blocks from the bus lines and a spare block can be connected to the bus in place of the defective block provided the bus is not defective. In these systems, switches are built into each block to provide the disconnect function. In more complex circuit designs, a relatively large number of buses are utilized to connect the components. In the extreme case, each pair of components is connected by a bus that runs just between those components.
Consider a case in which two components are connected by a local bus that runs only between those components. If one of the components fails, wiring in a spare component is difficult unless the spare is located close to the local bus. If the spare is located at a substantial distance, a new bus must be constructed to connect the spare to the original bus. Since providing new buses is difficult, such systems require the spare to be constructed adjacent to the component that it is to replace. This substantially increases the number of spare components that must be placed on the chip since any given spare can only act as a backup for a relatively small number of like parts, even though there are many other parts of that type in the SOC.
A second problem with these very large SOCs relates to the design of the buses themselves. If there are a large number of widely spaced components that are connected by buses dedicated to just those components, the routing of the buses on the chips becomes a complex design problem that further increases the cost of the SOC.
A third problem with SOCs that utilize a large number of local buses relates to the problem of testing the individual components. A spare cannot be inserted in place of a component if the components cannot be tested to determine those that are defective. In systems in which all of the components are connected via a single bus, the testing system can address each of the components separately provided the remaining components can be effectively disconnected from the bus. If, however, the SOC has a large number of local buses, the test system cannot access the individual components without going through other components unless a separate test bus is provided that connects all of the components that are to be tested. Such test buses require chip area and add complexity to the systems. After the devices have been tested, the test structure is of little use, and hence, represents wasted silicon area.
Systems in which a large number of processing blocks are connected to, and share, the same communication bus also suffer from bus contention problems. In such systems, the communication bus can become a bottleneck that limits the performance of the system.